Memory bank organization correlating distance with a memory map

Details Memory bank organization correlating distance with a memory map Memory bank organization correlating distance with a memory map

1998-05-12

2001-05-01

Ellis, Kevin L. (Department: 2751)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S154000, C711S005000

Reexamination Certificate

active

06226726

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to memory systems utilizing a plurality of memory banks with respect to a common processor. More particularly, it relates in one aspect to the assignment of enable signals and/or wait states to a plurality of memory banks to optimize the performance of a processing system.
2. Background of Related Art
The use of a plurality of memory banks within a processing system is common. For instance,
FIG. 5
shows a plurality of memory banks, e.g., fourteen memory banks
901
-
914
being accessed over a common address and data bus of a processor
900
.
In particular,
FIG. 5
shows a processor
900
in communication with fourteen memory banks
901
-
914
. The memory banks
901
-
914
may be any suitable size memory for the particular application. For instance, each of the memory banks
901
-
914
may be a 1K memory bank.
Conventionally, there is no particular rule utilized in assigning addresses to each of the individual memory banks
901
-
914
in the memory map of the processor
900
. For instance, frequently a simple sequencing through rows and/or columns of physical locations of the memory banks
901
-
914
on a circuit board or integrated circuit
920
is utilized to assign a plurality of memory banks as shown in FIG.
5
.
FIG. 5
shows the use of a conventional technique, i.e., arbitrary assignment, of memory banks
901
-
914
having a first memory bank
901
in a first row and first column assigned as memory bank No. 1. A second memory bank
902
in the first row and second column is arbitrarily assigned as memory bank No. 2, and the third memory bank
903
in the first row and third column is arbitrarily assigned as memory bank No. 3.
Similarly, the memory bank
904
in the second row and first column of memory banks
901
-
914
is assigned the next available memory address range, e.g., memory bank No. 4. The memory bank
905
in the second row and second column is assigned as memory bank No. 5, the memory bank
906
in the second row and third column is assigned as memory bank No. 6, and the memory bank
907
in the second row and fourth column is assigned as memory bank No. 7. The third row of memory banks
908
-
911
is assigned as memory banks No. 8 through No. 11, respectively, and the fourth row of memory banks
912
-
914
is assigned as memory banks No. 12 through No. 14, respectively.
FIG. 6
shows the resulting memory map of the processor
900
shown in
FIG. 5
, assuming as an example that each of the memory banks
901
-
914
are 1 kilobytes (1K) in length.
In particular, in
FIG. 6
, the memory bank
901
assigned as memory bank No. 1 will be accessed by the processor
900
in an address range of 0 up to 1K-1. (For simplicity, 1K-1, 2K-1, etc. will be referred to herein as 1K, 2K, etc.). The memory bank
902
assigned as memory bank No. 2 will be accessed by the processor
900
in an address range of 1K up to 2K. Similarly, the third memory bank
903
through the fourteenth memory bank
914
will be accessed in a contiguous and sequential memory range of the processor from 2K up to 14K. Ultimately, the assignment of the fourteen memory banks
901
-
914
in the memory map of the processor
900
provides the processor
900
with, e.g., contiguous or piecewise contiguous memory equal in length to the total length of all memory banks
901
-
914
, e.g., 14K of contiguous memory.
With arbitrarily or sequentially assigned memory banks
901
-
914
, e.g., as shown in
FIG. 5
, processing performance can be guaranteed only as fast as the slowest memory bank will allow. However, capacitance and resistance in the electrical connections between the processor
900
and the respective memory banks
901
-
914
slows down the electrical signals between the processor
900
, the line drivers, and the respective memory banks. This increases access time and decreases processing performance as the memory banks become physically/electrically more distant from the processor
900
and/or as the electrical lines between the processor
900
and the respective memory banks
901
-
914
increase in length.
To reduce the capacitance and/or resistance between the memory banks
901
-
914
and the processor
900
, conventional memory system designs locate the processor
900
as close as possible to the most distant memory banks, e.g., memory banks
907
and
911
as shown in the example of FIG.
5
. Nevertheless, reduction of the capacitance and/or resistance between the processor
900
and the farthest memory bank oftentimes pushes the envelope of current technology.
Thus, even presuming that the processor
900
on a circuit board or integrated circuit
920
is located as close as possible to the memory banks
901
-
914
, there will always be one or more memory banks, e.g., memory bank No. 7 or memory bank No. 11 as shown in
FIG. 5
, which will be more distant from the processor
900
, either physically and/or electrically, than another one of the memory banks, e.g., memory bank No. 4.
The inevitable result that at least one memory bank will be farther either physically and/or electrically from the processor
900
than another results in an unavoidable limitation on the processing performance of the system: that the processing performance will be limited to that between the processor
900
and the farthest memory bank, e.g., memory bank No. 7 as shown in the example of FIG.
5
. Accordingly, conventional processing systems improve overall performance by, among other things, utilizing sophisticated techniques to minimize the physical distance between a processor and the plurality of memory banks with which it will communicate.
Although continual technology advances allow smaller memory elements and closer compaction between memory elements providing shorter distances both electrically and physically to the processor as time goes on, conventional systems nevertheless fail to provide a performance any better than the worst case scenario of the memory system.
There is thus the need to improve processing performance given inevitable constraints when using a plurality of memory banks, e.g., that one memory bank will always be farther than another.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a processing system comprises a plurality of memory banks, and a processor having a memory map. Each of the plurality of memory banks is assigned in order to the memory map of the processor based on a respective physical distance or electrical distance to the processor.
In accordance with another aspect of the present invention, a processing system comprises a memory bank, and at least two processors adapted for operation at a similar frequency. Each of the at least two processors has a different number of wait states with respect to accesses to the memory bank.
A method of assigning a plurality of memory banks to a contiguous memory map of an accessing processor in accordance with the principles of the present invention comprises correlating an ordering of the plurality of memory banks in the contiguous memory map with an ordering of respective distances of the plurality of memory banks from the accessing processor.


REFERENCES:
patent: 5561825 (1996-10-01), Yamagami et al.
patent: 5946483 (1999-08-01), Boutaud et al.
IBM, “High-Speed Multi-Function Computer Clock Circuit With a Variable Frequency Output”, Jun. 1, 1984, vol. 27, Iss. 1B, p. 795-796, IBM TDB.

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