Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1999-08-31
2001-12-11
Kim, Matthew M. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S151000, C711S152000, C711S162000, C709S241000, C710S040000
Reexamination Certificate
active
06330647
ABSTRACT:
BACKGROUND
The invention relates generally to computer system memory access operations and, more particularly, to the allocation of memory access bandwidth based on an access count priority scheme. Each device requesting access to system memory may be assigned an access count—the value of which determines the number of consecutive memory access cycles the device may use before a different device is allowed an opportunity to access memory.
Many current computer systems employ memory sharing architectures in which a plurality of devices share access to, and use of, a common system memory resource. For example, the system memory of a personal computer (PC) is typically shared by one or more central processing units (CPUs), one or more Accelerated Graphics Port (AGP) devices, one or more Peripheral Component Interconnect (PCI) devices, one or more Universal Serial Bus (USB) devices, and one or more embedded devices such as bus-to-bus bridge circuits and digital signal processors.
In some prior art computer systems, memory access is controlled by a memory control device which arbitrates between various requestors (i.e., devices seeking access to system memory) in a round-robin fashion. In these systems, a first requester is granted a single access followed by a second requester and so on. When all requesters have been granted access once, the process repeats. A drawback to conventional round-robin based arbitration schemes is that it may take a unacceptably long time to completely service/satisfy a requester having a multiple memory access transaction. In some other prior art computer systems, memory access is controlled by a memory control device which arbitrates between various requestors based on a requestor's assigned priority. In these systems, higher priority requesters are favored over lower priority requestors. A drawback to conventional priority based arbitration schemes is that high priority requesters may block lower priority requesters from gaining access to system memory for an unacceptably long time.
As the number of devices issuing memory access requests increases, it becomes ever more important to allocate memory bus bandwidth (i.e., share system memory) in an efficient manner. Thus, there is a need for a memory access control technique that efficiently services requestors issuing multiple access transactions without denying access to those requestors issuing single access transactions and/or low priority requesters for an unacceptably long time.
SUMMARY
In one embodiment the invention provides a method to arbitrate computer memory request signals. The method includes selecting a first memory request signal (associated with a first requestor), associating an access count value with the first memory request signal, and allowing the first memory requester to access the computer memory access count value consecutive times. The method may be stored in any media that is readable and executable by a programmable control device.
In another embodiment, the invention provides a computer memory access control device comprising a memory controller to access a computer memory, a storage element adapted to receive an access count value, and an arbiter coupled to the memory controller and the storage element, the arbiter adapted to selectively couple one of a plurality of memory request signals to the memory controller for N consecutive memory access operations, wherein N is based on the access count value.
REFERENCES:
patent: 5212795 (1993-05-01), Hendry
patent: 5241644 (1993-08-01), Nomura et al.
patent: 5666516 (1997-09-01), Combs
patent: 5727150 (1998-03-01), Laudon et al.
patent: 5765197 (1998-06-01), Combs
patent: 5960468 (1999-09-01), Paluch
patent: 5987574 (1999-11-01), Paluch
patent: 6006303 (1999-12-01), Barnaby et al.
patent: 6024472 (2000-02-01), James et al.
patent: 6032232 (2000-02-01), Lindeborg et al.
patent: 6035377 (2000-03-01), James et al.
patent: 6035378 (2000-03-01), James
Jeddeloh Joseph M.
Larson Douglas A.
Kim Matthew M.
Micro)n Technology, Inc.
Peugh B. R.
Trop Pruner & Hu P.C.
LandOfFree
Memory bandwidth allocation based on access count priority... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory bandwidth allocation based on access count priority..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory bandwidth allocation based on access count priority... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2571379