Memory array write addressing circuit for simultaneously address

Static information storage and retrieval – Read/write circuit – Simultaneous operations

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Details

36523002, 36523003, 36523006, 36523008, G11C 800

Patent

active

052355454

ABSTRACT:
A semiconductor memory circuit which comprises a plurality of memory cells and a plurality of address lines. Each address line has a line address within a sequence of line addresses and is connected to address at least one corresponding memory cell for writing when the address line is activated. The memory circuit has a multiple address latching circuit for sequentially receiving at least two spaced coded line addresses within the sequence of line addresses and for simultaneously activating a series of address lines having line addresses between the spaced line addresses, inclusive, to address corresponding memory cells for writing. The memory circuit also has an address comparator so that the spaced coded addresses may be received in any order.

REFERENCES:
patent: 4845678 (1989-07-01), van Berkel et al.
Micron's MOS Data Book, Section 1 and Section 3, (1990/A) pp. 1-1 to 1-121 and 3-1 to 3-102.
Mitsubishi Data Book, Section 4 (video memory), (1990). pp. 4-3 to 4-145.
Electronic Design, "Speed Memory, Ease Timing Reqirements with VRAM Functions", by Mailloux et al. Nov. 23, 1989.

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