Memory array with switchable upper and lower word lines

Details Memory array with switchable upper and lower word lines Memory array with switchable upper and lower word lines

1981-12-30

1984-07-17

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

For complementary information

365154, G11C 1140

Patent

active

044609841

ABSTRACT:
Disclosed is a memory array in which each cell consists of a pair of cross coupled bipolar transistors with antisaturation clamps, a load resistor connected to the collector of each of the cross coupled transistors forming storage nodes, and Schottky barrier diode input/output devices connecting each node to a respective bit line. The emitters of the cross coupled transistors are connected to a lower word line while the load resistors are connected to an upper word line. Both the upper and lower word lines are switchable providing high speed as well as highly stable operation with very low power supply voltage requirements.

REFERENCES:
patent: 3969707 (1976-07-01), Lane et al.
patent: 4164791 (1979-08-01), Homma
patent: 4193127 (1980-03-01), Gersbach
F. C. Wernicke, "Circuit Concept for Rapidly Reading and Writing Semiconductor Storages With Diode-Coupled Cells," IBM Technical Disclosure Bulletin, vol. 25, No. 6, Nov. 1982, pp. 2746-2750.
Wiedmann, IBM Technical Disclosure Bulletin, Aug. 1970, pp. 616-617, "Memory Cell".
Berger et al., IBM Tech. Bulletin, May 1974, pp. 3965-3967, "Content Addressable Storage Cell."
Lynes et al., IEEE J. Solid State Circuits, V. SC-5, pp. 186-191, Oct. 1970, "Memory Using Diode-Coupled Bipolar Transistor Cells".

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