Memory array with sequential row and column addressing

Details Memory array with sequential row and column addressing Memory array with sequential row and column addressing

1979-01-29

1980-10-28

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Signals

365239, G11C 800, G11C 700

Patent

active

042311101

ABSTRACT:
An electronic memory comprises a plurality of memory cells arranged in an array of rows and column, row address circuitry, column address circuitry, circuitry for sensing the logic states of the cells, and circuitry for delaying addressing of a selected column until after an addressed row has achieved a voltage level suitable for the sensing circuitry to sense. By so delaying the addressing of the selected column, the time required to read information out is reduced substantially--typically by a factor of two for a 1K or 2K.times.8-bit static memory.

REFERENCES:
patent: 3509548 (1970-04-01), Sinden
patent: 3832699 (1974-08-01), Matsue

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