Memory array with redundant elements

Details Memory array with redundant elements Memory array with redundant elements

1981-10-08

1983-12-20

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Bad bit

365 72, 365185, 371 10, G11C 700

Patent

active

044221614

ABSTRACT:
A memory array formed on a single chip is provided with at least one redundant column (or row) of memory cells in addition to "standard" number of columns and rows where the spare column (or row) of cells is designed to be substituted for a standard column (or row) found to have defective cells. Programmable non-volatile electrically alterable elements are connected to the column (or rows) conductors of the standard and redundant columns (or rows) of cells for selectively disconnecting from the memory circuit a standard column (or rows) containing defective cells and substituting therefor a redundant column (or row) of cells.

REFERENCES:
patent: 3753235 (1973-08-01), Daughton et al.
patent: 3753244 (1973-08-01), Sumilas
patent: 3755791 (1973-08-01), Arzubi et al.
patent: 4047163 (1977-09-01), Choate et al.
patent: 4051354 (1977-09-01), Choate
patent: 4228528 (1980-10-01), Cenker et al.
Chin et al., "Reversible On-Chip Redundancy Scheme," IBM Tech. Disc. Bul., vol. 14, No. 10, 3/72, pp. 2983-2984.

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