Memory array with memory cells having reduced short channel...

Details Memory array with memory cells having reduced short channel... Memory array with memory cells having reduced short channel...

2005-11-08

2005-11-08

Le, Dung A. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S314000, C257S315000, C257S316000, C257S317000, C438S257000, C438S258000, C438S593000

Reexamination Certificate

active

06963106

ABSTRACT:
According to one exemplary embodiment, a method for fabricating a floating gate memory array comprises a step of removing a dielectric material from an isolation region situated in a substrate to expose a trench, where the trench is situated between a first source region and a second source region, where the trench defines sidewalls in the substrate. The method further comprises implanting an N type dopant in the first source region, the second source region, and the sidewalls of the trench, where the N type dopant forms an N+ type region. The method further comprises implanting a P type dopant in the first source region, the second source region, and the sidewalls of the trench, where the P type dopant forms a P type region, and where the P type region is situated underneath the N+ type region.

REFERENCES:
patent: 5518942 (1996-05-01), Shrivastava
patent: 6410389 (2002-06-01), Cappelletti et al.

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