Memory array with a delayed wordline boost

Details Memory array with a delayed wordline boost Memory array with a delayed wordline boost

2007-10-30

2007-10-30

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S189090, C365S194000, C365S226000

Reexamination Certificate

active

11191349

ABSTRACT:
Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.

REFERENCES:
patent: 5276652 (1994-01-01), Anami
patent: 6405277 (2002-06-01), Jen et al.
patent: 6639826 (2003-10-01), Houston
patent: 7120076 (2006-10-01), Sugahara

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