Memory array test circuit and method

Details Memory array test circuit and method Memory array test circuit and method

1997-11-26

1999-08-31

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365194, G11C 700

Patent

active

059462450

ABSTRACT:
A circuit for testing a memory cell array 100. The circuit includes a test circuit 104 coupled to the array and includes a data output line 106 and a failure signal output line 108. A shift register 110, which includes a plurality of latches, a clock signal input 114, and an output line 116, is connected to the failure signal output line of the test circuit. The circuit also includes a three-state output buffer driver 118, the buffer driver including a data input line, a failure signal input line, and a data output line. The failure signal line of the buffer driver is connected to the output line of the shift register 110. Upon detecting a defective memory cell in the array, the test circuit produces a failure signal on the failure signal output line 116 of the test circuit. The failure signal is then sent to the shift register 110 causing the buffer driver 118 to enter a high-impedance state in response to said failure signal. The shift register 110 comprises a number of latches in accordance with the desired latency variability of the system or test equipment using the test circuit.

REFERENCES:
patent: 5477492 (1995-12-01), Ohsaki et al.
patent: 5777942 (1998-07-01), Dosaka et al.
patent: 5812472 (1998-09-01), Lawrence et al.

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