Memory array system

Details Memory array system Memory array system

2002-03-11

2004-04-27

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S189070, C365S189050, C365S236000, C365S230010

Reexamination Certificate

active

06728156

ABSTRACT:

TECHNICAL FIELD
The present invention relates in general to memory array systems and more particularly to versatile memory array systems that can be used in a variety of applications.
BACKGROUND OF THE INVENTION
Computer systems incorporate volatile memory devices such as dynamic random access memories (DRAMs) to store digital data used by the system. Memory arrays are groups of memory cells organized as rows and columns wherein each memory cell contains one bit of data. The technology used to design memory devices has advanced so that more and more data can be stored on a single memory device chip.
In a memory array, the rows are selected by row decoders that are typically located adjacent to the end of the row lines. Each of the row lines is electrically connected to the row decoders so that the appropriate signals can be received and transmitted. The columns of the memory array are connected to input/output devices such as a read/write multiplexer. In the case of DRAMs, the memory array columns are also connected to line pre-charging sense amplifier circuits at the end of each column line.
In order to store data in the DRAM or to access stored data, it is necessary to specify a storage location on the memory array. A row address and column address are provided from an external source to decoders so that a word line and a sense amplifier can be selectively activated in order to read from or write to a desired portion on the memory array.
There is a need to be able to detect certain errors that can occur within a memory cell which is no longer functioning properly. Early memory chips were organized so that each chip provided one-bit of data for each address. Currently memory chips frequently are organized into sets of 4-bits of data for each address. If one of these memory chips fails the result is potentially erroneous data bits. Therefore, the error correction code needs to be designed for 4-bit error detection.
Incorporating a 4-bit error detection and 1-bit correction code in a 64 or 128-bit memory system would require eight or nine check bits. Modern memory buses are often 64 or 128-bits wide. Currently memory arrays are frequently used in personal computers which are requiring 32 MB to 256 MB memory systems. Presently memory arrays typically contain 256 megabit devices and the trend is towards production in memory arrays that will contain 1-4 gigabits within 2 to 4 years.
With the anticipated increase in memory array sizes, the present approach of utilizing 1 or 4-bit wide memory chip organization is being reconsidered. For example, employing the present 1 or 4-bit memory chip organization with the 32-bit wide dataword will require a 32 memory array with 1-bit organization or 8 memory arrays with 4-bit organization. This will, in turn, result in a minimum granularity of 8 GB or 4 GB respectively. This large amount of memory in a computer system such as a desktop or laptop is excessive and unnecessary and will increase the overall cost of the system. In response to the minimum granularity problem, memory array manufacturers are moving to 8, 16 and even 32-bit wide memory organization schemes with a corresponding increase in the number of bits required for array detection and correction. Accordingly, what is also needed is an improved error detection technique that minimizes the cost, the system and the extra amount of bits required in detecting and correcting errors. Such a system is provided in U.S. patent application Ser. No. 09/716,915 hereby incorporated by reference.
The contents of the volatile storage devices such as DRAMs fade overtime. Refresh operations are used to periodically rewrite the date into each memory cell. During a refresh operation, the contents are stored temporarily in the sense latch, a buffer, or a register and then rewritten into the same address where it previously was stored so that it is fresh. The timing for the refresh operation is dependent on the system. A refresh address counter keeps track of which row is to be refreshed during a refresh cycle. A memory cell connected to the word line which is selected with the refresh address is refreshed during the operation.
Refreshing the DRAM requires power consumption which puts a stress on the power requirements of the overall system. Therefore, it is desirable to be able to minimize the frequency of refreshes while ensuring that the data is not lost by disappearing before the memory cell is refreshed. There are fluctuations in the amount of time that a given memory cell can hold its charge to maintain the data, which varies from cell to cell. Therefore, it would be desirable to optimize the power consumption of a DRAM by using the cells in the DRAM that can go for longer periods without being refreshed
In general, the goal is to minimize the size and cost of the DRAM systems. Another goal is to provide flexibility so that a DRAM can be initially designed and built for general use and can later be designated for a particular purpose, such as a hand held device and a Palm computer. A Palm computer system, for example, has certain temperature and battery power requirements which can effect refresh interval requirements. A Palm computer also has specific requirements regarding power consumption limitations.
The temperature of the system in which the DRAM will be placed and power consumption limitations have an effect on how often a refresh operation needs to be performed. A DRAM can be optimized for a specific system by using those word lines or memory cells with the greatest capacity to endure certain temperatures without losing data or without requiring refresh cycles as frequently.
Even after the system is installed in a system, use of DRAMs having extra wordlines and memory cells that can be selectively activated would provide greater flexibility. It is also desirable that the swapping out of a defective memory cell be done without system intervention, without increasing the chip size, performance penalties and the cost of the chip.
It is desirable that the on-chip error detection be performed without system intervention since the retention time is very strongly coupled to the temperature and the cell signal strength is strongly related to other external environmental conditions. Use of a DRAM chip in an external system alters the temperature of the memory cell so the true tolerance level can be found. It is preferable for the DRAM system to monitor failure and adjust the refresh interval time between refresh cycles accordingly. This would allow the system to increase the interval during periods of inactivity when the device is cooler and other environmental conditions are favorable. This would, in turn, reduce the power consumed by the device.
Finally, it is desirable for a device to use its own error signal to adjust its own self-refresh interval. A single part number could be used to satisfy low power and standard applications. It is desirable for the memory unit to self-regulate its refresh interval, thereby minimizing power consumption. The need to sort by power requirements would be eliminated allowing the use of a generic part number.
One or more of the foregoing problems is solved and/or one or more of the foregoing needs is met by the present invention.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved memory array system. It is another object of the preferred embodiment of the invention to provide a system and method for detecting failures in a memory array. It is a further object of the preferred embodiment of the invention to provide a memory array system that can be flexibly adapted for use in a variety of applications with varying power consumption and temperature requirements.
A memory array system is provided comprising a plurality of rows of memory cells, each row having an address, wherein each memory cell stores volatile data requiring periodic refreshing. A refresh controller controls the periodic refreshing of data in each row of memory cells. A refresh address counter indicates the address of the row of cells for refreshing. A temp

Affiliated with

Also associated with

Rating

Memory array system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory array system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory array system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3254674