Memory array size reduction

Details Memory array size reduction Memory array size reduction

1992-07-29

1994-01-04

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Differential sensing

36523005, 365190, G11C 700

Patent

active

052766500

ABSTRACT:
An apparatus and method for reducing the size of memory arrays which are comprised of memory cells which use bit lines to access the cells. Adjacent cells in a row are assigned different word lines so that bit lines between adjacent cells can be shared. During the read and write cycles, bit lines of a row are selected by alternating the word lines and by setting corresponding sense amplifier selectors. By sharing bit lines in this way, the size of the memory array can be decreased significantly. Therefore, using the teachings of the present invention, a given amount of memory can be manufactured in a significantly smaller area. Alternately, significantly more memory can be stored in the same amount of area as would be required using a usual memory design.

REFERENCES:
patent: 4954987 (1990-09-01), Auvinen et al.

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