Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-02-02
2002-06-18
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S210130
Reexamination Certificate
active
06407953
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits having memory cells arrays, and particularly to three-dimensional arrays incorporating multiple levels of memory cells.
2. Description of the Related Art
Manufacturers of integrated circuits that include write-once memory arrays (also known as one-time programmable, or OTP memory arrays) face a difficult test problem. The memory cells of the array must be assured of being successfully programmed by a subsequent user, but the manufacturer cannot program the memory cells during the testing procedures to confirm that each memory cell can be programmed, because the memory cells, once written, cannot be re-written or erased before shipping to an end user of the integrated circuit.
Traditionally, several techniques have been utilized to increase the assurance level that a memory array, once shipped, will indeed be programmable by an end user. In one such technique, extra memory cells may be implemented outside the memory array whose characteristics may be measured and which may be programmed during a manufacturer's test procedures to confirm generally the integrity of the memory cells on each integrated circuit die. Such extra memory cells may be implemented individually in the periphery of an integrated circuit, or may be implemented as a small test memory array in the periphery of an integrated circuit, or may be implemented in a dedicated test die which is occasionally stepped into the wafer, or even implemented in the scribe streets between individual integrated circuit dies on a wafer. While such a structure may provide adequate general characterization of the memory cells formed nearby, it provides no assurance against individual defects that may affect isolated memory cells or individual rows or columns of memory cells.
Because of the inability to provide total assurance of a memory array, manufacturers sometimes warranty a device to be fully programmable for at least a specified percentage of the memory cells. For example, a memory device may carry a warranty to be at least 98% programmable, or the device may be returned for credit. While this scheme protects an end user from the cost of buying a defective part, in essence the final test function has been shifted to the end user, who must either accommodate devices having an unpredictable capacity, or must be prepared to return defective devices.
With the increasing importance of write-once memory devices, there remains a continued need for improved techniques for testing devices that include a write-once memory array.
SUMMARY OF THE INVENTION
In an integrated circuit having a memory array, a short between a word line and an adjacent word line may be detected by biasing adjacent word lines to different voltages, and detecting any leakage current flowing therebetween. If the current is higher than what would be attributable to leakage currents through normally behaved memory cells, and any other expected source of leakage current, the word lines may be deemed to be shorted together. Individual word lines may be sequentially biased to a first voltage, with all other word lines biased to a second voltage different from the first voltage, which allows a shorted word line to be localized within the array. Alternatively, groups of alternating word lines may be biased to the first voltage, and the adjacent word lines biased to the second voltage, to more quickly determine if a shorted word line exists anywhere within the group of word lines.
Shorted bit lines may be determined in like manner. A short between a bit line and an adjacent bit line may be detected by biasing adjacent bit lines to different voltages, and detecting any leakage current flowing therebetween. The bit lines may be biased to a first voltage individually, or in groups of alternating bit lines (i.e., every other bit line in a group). As with detecting word line shorts, a current detector may be implemented in any of several convenient points within a current path formed by the shorted word line or bit line. Such a detector may respond with an output signal whenever the detected current exceeds a predetermined value, or may be implemented as a measurement circuit to quantify the magnitude of the current.
A short between one or more word lines on a given layer or level of the memory array and one or more bit lines on an adjacent layer of the memory array may also be detected by biasing the word lines to a different voltage than that to which the bit lines are biased. In a three-dimensional memory having at least more than one layer of word lines and/or more than one layer of bit lines (i.e., having at least two layers of memory cells, each formed between a word line layer and a vertically adjacent bit line layer), inter-layer word line shorts may also be detected by biasing word lines on different layers to different voltages and detecting any unexpected leakage current.
The above stated techniques for detecting either intra-layer shorts on word lines and/or bit lines, inter-layer shorts between word lines and bit lines, or between different layers of word lines or different layers of bit lines, arguably presume that each such word line or bit line is continuous across the memory array so that a short located, for example, at a “far end” of a word line (relative to its driver or biasing circuit) can therefore be actually detected. If an “open” (i.e., an open circuit) exists in such a word line that is shorted to its neighbor, the short could not be detected if located “beyond” the location of the “open.”
However, a word line may be confirmed to be continuous across a memory array by programming a memory cell located at the far end of the word line relative to its programming driver. A test bit line is preferably included in the array which provides a respective test memory cell between each respective word line and the test bit line, and which is preferably located along the side of the memory array opposite the word line drivers for the respective word lines. If each test memory cell in the test bit line can be successfully programmed, this ensures that each word line is continuous (i.e., has no “opens” in it) and also confirms that each word line's programming driver is functioning properly. Moreover, it also ensures that the metallization or other conductive material forming the word line has a low enough impedance to pass an adequately high voltage all the way across the memory array to the test memory cell being programmed, and further can carry enough current across the memory array to adequately program the test memory cell.
Similarly, a test word line is preferably included in the array which provides a respective test memory cell between each respective bit line and the test word line, and which is preferably located along the side of the memory array opposite the bit line drivers for the respective bit lines. If each test memory cell in the test word line can be successfully programmed, this ensures that each bit line is continuous and that each bit line's programming driver is functioning properly. Moreover, it also ensures that the metallization or other conductive material forming the bit line has a low enough impedance to develop an adequately high voltage across the test memory cell located all the way across the memory array, and further assures that the bit lines can carry enough current across the memory array to adequately program the test memory cell.
If the corresponding test memory cell on the far end of each word line and bit line in the array is successfully programmed, which confirms the continuity of each of the word lines and bit lines, then the shorts test described earlier can be deemed to have confirmed that no shorts exist within the entire memory array. Moreover, every programming driver circuit for both word lines and bit lines is also confirmed to be functional. If memory cells in the regular memory array are read, every bit in the array can be verified to have not been inadvertently programmed d
Matrix Semiconductor Inc.
Nguyen Tan T.
Zagorin, O′ Brien & Graham, LLP
LandOfFree
Memory array organization and related test method... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory array organization and related test method..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory array organization and related test method... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2947095