Memory array incorporating two data busses for memory array...

Details Memory array incorporating two data busses for memory array... Memory array incorporating two data busses for memory array...

2006-07-31

2008-12-09

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bidirectional bus

C365S230060, C365S230040, C365S230030, C365S163000, C365S148000

Reexamination Certificate

active

07463536

ABSTRACT:
Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.

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