Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-02-12
2002-04-16
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S226000, C365S230060
Reexamination Certificate
active
06373753
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and particularly to those driving a selected word line in a memory array to a boosted voltage level.
2. Description of Related Art
Semiconductor random-access memory devices or sub-systems using arrays of dynamic memory cells (e.g., 1-transistor/1-capacitor (1T/1C) cells) have consistently provided greater density and lower cost per bit than those using static memory cells (e.g., 6-transistor (6T) cells, or 4-transistor/2-resistor (4T/2R) cells). However, such dynamic random-access memory arrays have historically also been lower in performance when compared to static random-access memory arrays. Consequently, system designers have typically chosen dynamic memory arrays (e.g., commercially available dynamic random access memories, or DRAMs) when high density and low cost are required, such as for CPU main memory applications. Conversely, designers have typically chosen static memory arrays when the highest possible performance is required, such as for cache memory and high speed buffer applications. Examples of static memory array devices or sub-systems include commercially available static random access memories (SRAMs) and CPU-resident on-board cache memory sub-systems.
The reasons often cited for the lower performance of dynamic memory arrays include the destructive sensing of all memory cells common to the addressed word line (encountered in virtually all dynamic memory arrays) and the consequential need to restore data back into each sensed memory cell during the active cycle, the need to equilibrate bit lines and various other differential nodes and to precharge various circuit nodes between active cycles, and the requirement for periodic refreshing of all dynamic memory cells.
Traditionally, N-channel dynamic memory arrays have provided for boosting a selected word line to a voltage above the VDD power supply voltage. Moreover, a high-going bit line is usually restored to a fall VDD level by the bit line sense amplifier. If the selected word line is boosted to a voltage that is more than an NMOS threshold voltage above VDD, then a selected memory cell coupled to the high-going bit line can be restored to a fall VDD voltage level. Many techniques may be employed to generate such a boosted voltage, but inevitably most techniques rely on a capacitively-coupled method which results in a boosted voltage that is a ratio of VDD. If, at low VDD, a boosting capacitor is adequately sized to generate a boosted voltage sufficiently greater than a threshold voltage above VDD, then at high VDD the same size capacitor provides a boosted voltage that is higher than VDD by far more than a threshold voltage. The additional voltage stress placed upon devices within the integrated circuit can degrade the reliability of the integrated circuit, or alternatively would place more stringent requirements on the semiconductor process to be able to safely tolerate such higher voltages. As both the horizontal and vertical dimensions of devices continue to shrink, it is increasingly difficult and performance sacrificing to fabricate a semiconductor process that is capable of tolerating such variation of maximum voltage.
SUMMARY OF THE INVENTION
To provide for an internally-generated boosted voltage without such wide voltage extremes, a VPP voltage is internally generated by a charge pump type circuit whose output is a substantially fixed voltage which is regulated with respect to VSS (i.e., ground). It is substantially independent of VDD over process and environmental variations. The VPP voltage is used by the row decoders to drive a selected word line from VSS to VPP, and preferably to boost selected array select signals from VDD to VPP, rather than driving the selected word line to VDD or to a voltage which is a ratio of VDD.
For typical operating voltages, the VPP voltage is somewhat higher than VDD, although at low operating voltage the VPP voltage may be substantially higher than VDD, while at very high operating voltage, the VPP voltage may be similar in magnitude to the VDD voltage. Preferably the VPP voltage is chosen to be near the maximum voltage that the field effect transistors (FETs) can safely tolerate. Since the VPP is regulated to be substantially independent of variations in the VDD voltage, at low operating voltage the VPP level is advantageously at a higher voltage than would otherwise be safe, and tolerances in the VPP voltage level which would otherwise be necessary to account for variations in the VDD level are unnecessary.
In a preferred embodiment, the VPP generator includes a plurality of pump circuits, each connected to the VPP output, and each controlled by a common control circuit. Each such pump circuit is enabled to pump according to the amount of charge which is needed at a particular time, based on the measured level of both VDD and VPP. A first regulator compares various fractions of the VDD voltage to an internally generated bandgap voltage, while a second regulator compares various lower fractions of the VPP voltage to the bandgap voltage. If VDD is low, then more of the pump circuits are enabled for a given cycle (or alternatively, enabling one or more pump circuits having a higher aggregate pumping capacity). As VDD increases, fewer such pump circuits are enabled. Similarly, if VPP is particularly low (such as during power-up), then all the pump circuits are enabled, while if VPP is already high enough, then none of the pump circuits are enabled. In a preferred embodiment, none of the pump circuits are enabled if VPP exceeds 4.0 volts, while all of the pump circuits are enabled if VPP is less than 3.8 volts. Between 3.8 and 4.0 volts, the measured values of both VPP and VDD determine how many and what pumping capacity of pump circuits are enabled.
For a given VPP and VDD voltage there are a fixed number of pump circuits enabled. As VDD increases slightly, the charge per cycle increases, even though the same number of pump circuits are enabled, because the VDD is increasing. However, as VDD further increases slightly, one less pump is enabled, so the charge per cycle abruptly decreases. Then as VDD further increases, the charge per cycle again increases because VDD is increasing. When plotted as a function against VDD, the charge per pump cycle thus appears as a sawtooth waveform, which decreases abruptly as each such pump circuit is successively disabled. The pump circuits are preferably not uniformly sized, but instead each size determined individually so that the charge per pump cycle, when plotted as a sawtooth waveform against VDD, varies from min-to-max as little as possible over the range of VDD.
A significant amount of internal de-coupling (i.e., filtering) capacitance on the VPP node is provided by the various row decoder and array select circuits which are unselected during a given cycle. For example, the last two buffers within each row decoder provide in aggregate a large effective capacitance. Taken together, such capacitances provide a significant reservoir of charge on the VPP node without requiring separate devices or structures. A test control signal preferably causes the regulated value of VPP to decrease by a small amount (e.g., 200 mV) when in certain test modes to ensure reliable operation of the memory device when VPP is actually lower than the minimum expected VPP voltage. By using such test modes, adequate operating margins for normal operation may be more easily assured.
If the semiconductor technology allows, transistors which are exposed to the VPP level (e.g., transistors whose gate terminal is driven at any time to the VPP level while the source or drain terminal might be at ground, such as the memory array access transistors and various array select transistors, or those transistors whose drain or source terminal is driven at any time to the VPP level while the gate terminal might be at ground) are preferably implemented using a thicker gate dielectric than the majority of the other transistors which are never exposed to such
Mai Son
Zagorin O'Brien & Graham LLP
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