Memory array having redundant word line

Static information storage and retrieval – Read/write circuit – Bad bit

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Details

36523003, 36523006, G11C 2900

Patent

active

055684335

ABSTRACT:
Multiselection of word lines is eliminated in a memory array which includes a word line generation circuit which inhibits line selection until a latest address bit is received.

REFERENCES:
patent: 4365319 (1982-12-01), Takemae
patent: 4723227 (1988-02-01), Murotani
patent: 4745582 (1988-05-01), Fukushi et al.
patent: 4858192 (1989-08-01), Tatsumi et al.
patent: 4905192 (1990-02-01), Nogami et al.
patent: 4951253 (1990-08-01), Sahara et al.
patent: 5107464 (1992-04-01), Sahara et al.
patent: 5235548 (1993-08-01), Kurkowski
patent: 5276360 (1994-01-01), Fujima
patent: 5327380 (1994-07-01), Kersh, III et al.

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