Memory array having redundant word line

Details Memory array having redundant word line Memory array having redundant word line

1997-08-26

1998-08-18

Santamauro, Jon

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 10, 326 98, H03K 19003, G11C 800

Patent

active

057962715

ABSTRACT:
An address gating circuit for a memory array having redundant word lines. The address gating circuit includes a plurality of address lines comprising paired true and complement address lines for receiving address bits. The true and complement values of the address lines are ORed together then the results are ANDed together to generate an output. The output is used to inhibit selection of one of the address lines until a latest address bit is received.

REFERENCES:
patent: 4401903 (1983-08-01), Iizuka
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5117133 (1992-05-01), Luebs
patent: 5208489 (1993-05-01), Houston
patent: 5258666 (1993-11-01), Furuki
patent: 5550490 (1996-08-01), Durham et al.

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