Memory array having dummy cells implemented using standard array

Details Memory array having dummy cells implemented using standard array Memory array having dummy cells implemented using standard array

1997-07-24

1998-12-15

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Differential sensing

365203, 365205, 365206, G11C 700, G11C 1300

Patent

active

058503668

ABSTRACT:
A memory array (10) implemented by an integrated circuit is provided. The memory array (10) includes a bank of standard array cells (12) arranged in rows and columns. The bank of standard array cells (12) includes a plurality of rows of array cells (14) operable to provide memory storage and a plurality of rows of dummy cells (16) operable to provide a reference voltage level. A row decode block (22) is coupled to the bank of standard array cells via a plurality of wordlines (18) which include array cell wordlines and dummy cell wordlines. A sense amplifier block (24) is coupled to the bank of standard array cells (12) via a plurality of bitlines (20). The sense amplifier block (24) includes a plurality of sense amplifiers (26) coupled to the bitlines. The memory array (10) is operable to charge the plurality of dummy cells (16) to a precharge voltage level during a bitline (20) precharge period such that the dummy cells (16) operate to provide a reference voltage and capacitive balance to the sense amplifiers (26) when sensing an array cell (14).

REFERENCES:
patent: 5226014 (1993-07-01), McManus
patent: 5299165 (1994-03-01), Kimura et al.
patent: 5339274 (1994-08-01), Dhong et al.
patent: 5475642 (1995-12-01), Taylor
patent: 5477484 (1995-12-01), Nakashima
patent: 5640350 (1997-06-01), Iga

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