Memory array bitline timing circuit

Details Memory array bitline timing circuit Memory array bitline timing circuit

1999-06-14

2001-01-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S203000

Reexamination Certificate

active

06172925

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to memory systems and, more particularly, to circuitry for accurately clocking data from static random access memory.
2. History of the Prior Art
A static random access memory (SRAM) array stores data for use by some form of digital processing apparatus. A typical use of such memory is as some form of cache memory for a microprocessor. Such memories are typically used to provide data to a microprocessor because they can be accessed much more rapidly than main memory. Consequently, as processor speeds increase, the speed at which a static random access memory can be accessed must also increase.
In order to read data in an SRAM array, an interrogating signal is placed on a wordline connecting to the memory cells of a particular row of the memory and wordlines are placed in an interrogating condition. This causes signals to be placed on bitlines connecting to the columns being interrogated. The bitline signals are detected by sense amplifiers associated with each column. Typically, the memory cell data develops very slowly, and sense amplifiers are utilized to accelerate this operation. A clock activates the sensing amplifiers after a period from the initiation of the interrogation signals chosen to allow a sufficient signal to develop at each sense amplifier, and the signal developed by each sense amplifier is clocked to its output.
As the speed of operation of computers increases, the speed at which data must be read from the sense amplifiers increases so that the time at which the clock signals are applied becomes critical. If the timing signal appears too soon before the signals on the bitlines have had time to develop correctly, incorrect output signals can be produced. If the timing signal appears too late, then the performance of the microprocessor slows. As a practical matter, the speed of operation of computer microprocessor circuits has become so rapid that it is quite difficult to generate accurate timing signals for SRAM memories.
This becomes a particularly difficult problem when SRAM memory arrays for a microprocessor are produced by different manufacturers. The particular processes used in manufacturing a SRAM array define the signal transit times through the array and the time required to build sufficient signal level at the sensing amplifiers of the array. Different manufacturing processes often produce arrays which respond quite differently. An array produced by one process may function correctly with a particular processor while an apparently identical array produced by another process may not function at all with the processor.
It is desirable to provide a new circuit for generating very accurate timing signals for the sensing amplifiers of SRAM memory arrays.
SUMMARY OF THE INVENTION
The present invention is realized by a circuit for generating timing signals for clocking the sensing amplifiers of a SRAM memory array having a plurality of memory cells joined in rows by wordlines and in columns by bitlines comprising a dummy bitline, a plurality of memory cells joined to the dummy bit column, means for accessing a plurality of the memory cells in parallel to generate a bitline charging current significantly greater than a bitline charging current in a typical operative column of the SRAM memory array, a circuit responsive to current in the dummy bitline for generating a timing signal to sense amplifiers for generating output signals from memory cells of operative columns of the SRAM.
These and other features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.


REFERENCES:
patent: 5881008 (1999-03-01), Becker
patent: 5883834 (1999-03-01), Becker et al.
patent: 5966338 (1999-03-01), Liu et al.

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