Memory array architecture for a memory device and method of...

Details Memory array architecture for a memory device and method of... Memory array architecture for a memory device and method of...

2008-07-01

2010-11-30

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S063000, C365S185110, C365S185120, C365S185170

Reexamination Certificate

active

07843731

ABSTRACT:
A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells.

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