Memory array architecture for a memory device and method of...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185050, C365S104000

Reexamination Certificate

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07408806

ABSTRACT:
A high integration memory array architecture of the present invention includes a memory cell array including memory cells arranged in a predetermined configuration, and selection transistors having different threshold voltages so as to select a memory string of the memory cell array. By applying a proper bias voltage to the selection transistors, specific memory strings can be selected, so that operations for the memory array can be performed without intervening with adjacent memory cells.

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