Memory array architecture

Details Memory array architecture Memory array architecture

2001-04-24

2002-07-16

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000

Reexamination Certificate

active

06421267

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory, and more particularly to a memory array architecture which can reduce the coupling effect between bit lines and improve the performance of memory.
BACKGROUND OF THE INVENTION
Memory arrays are well known in the art and comprise matrices of memory cells organized into rows and columns. Each memory cell (or called memory transistor) comprises a gate, a source and a drain, each of which has to receive voltage in order for the cell to be accessed. Columns of sources and columns of drains are connected together by bit lines while rows of gates are connected together by word lines. To activate a cell, one word line, one source bit line and one drain bit line must receive voltage.
Various memory array architectures are developed which reduce the size of the memory array area by reducing the number of metal lines. In virtual ground architectures, the common ground line is eliminated. Instead, the drain of one cell serves as the source for its neighboring cell. To further reduce array size, the alternate metal virtual ground architecture (AMG), disclosed in U.S. Pat. No. 5,204,835, uses two bit lines per metal line. Typically, in the AMG architecture, the cell size is close or equal to the minimum feature size possible for the cell.
In the array architecture with such high integration, the distance between two adjacent bit lines is close or equal to the critical dimension of semiconductor process. As the critical dimension is scaled down under 0.18 &mgr;m, inductive-capacitive coupling effect will be occurring because of short distance between adjacent bit lines, and thereby prolongs time of memory read operation or causes an error signal occur, which results in a data accessing error.
Referring to
FIG. 4
a,
during reading operation of memory, bit line BL is pulled to high voltage level after address transition detection (ATD). However, signal sense line SENSEB must wait the bit line BL to be ready and stable, and then be shifted to low voltage level to start select line SL. This will increase reading time as accessing storage data, and read performance of memory will be therefore decreased.
Referring to
FIG. 4
b,
since the voltage on the select line SL is about several tens mV, the voltage on the select line SL will be disturbed by coupling effect of bit lines if signal sense line SENSEB is shifted to low voltage level when the bit line BL is still unready or non-stability. Little change of voltage on the select line SL will cause the sense amplifier sensing error, and data “0” or “1” stored in the memory cell will be read error. Hence, above-mention cases both heavily affect the working range of sense amplifier on the select line SL.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a memory array architecture, which can effectively improve the coupling effect between bit lines, and hence, increase sense accuracy and data reading speed.
The present invention provides a memory array architecture of which comprises a plurality of memory cells. A plurality of select transistors including upper and lower block select transistors is connected to the memory cells. A plurality of bit lines is connected to the select transistors, wherein odd bit lines connected to the upper block select transistors are located in a first metal layer, and even bit lines connected to the lower block select transistors are located in a second metal layer. Adjacent bit lines are in different metal layers. The memory cells can be selected from the following types of memory cells: read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), Flash EEPROM, nitride ROM (NROM), dual bit ROM and dual bit NROM.
The present invention also provides a memory array architecture of which comprises a plurality of memory cells. A plurality of select transistors, which including first upper and lower block select transistors, and second upper and lower block select transistors, is connected to the memory cells. First, second, third and fourth bit lines parallel to each other are connected to the select transistors. Wherein, the first and second bit lines are alternatively interlocated between the third and fourth bit lines. The first bit line is connected to the first upper block select transistors. The second bit line is connected to the first lower block select transistors. The third bit line is connected to the second upper block select transistors. The fourth bit line is connected to the second lower block select transistors. The distance between the bit lines of the present invention for memory cell accessing is increased, and the coupling effect between bit lines can be reduced. Therefore, sense time for data reading can be shortened, and sense accuracy also can be improved.


REFERENCES:
patent: 5557124 (1996-09-01), Roy et al.
patent: 5590068 (1996-12-01), Bergemont
patent: 5973691 (1999-10-01), Park et al.
patent: 6285574 (2001-09-01), Eitan

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