Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2002-06-28
2003-08-26
Phan, Trong (Department: 2818)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S156000, C365S230060
Reexamination Certificate
active
06611451
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to a memory array and wordline driver with supply voltage differential in standby.
BACKGROUND OF THE INVENTION
Maintaining SRAM arrays in a low power standby mode is becoming increasingly important both because of the increasing size (number of bits) of embedded SRAM and because of the increasing leakage of transistors as technology is scaled. Scaling to shorter gage length leads to use of thinner gate dielectrics, which in turn leads to use of lower voltages. Performance is reduced with lower voltage, leading to use of lower threshold voltages, and resulting higher subthreshold current.
One approach to reduce SRAM array leakage in standby is to raise the array lower supply voltage (Vss-array) This reduces the array leakage both by reducing the voltage across transistors in the array and by effectively applying a back-gate bias on the n-channel transistors, raising their threshold voltage. Initially, it might be considered an advantage to keep the off wordlines at the substrate voltage, putting a negative gate-to-source voltage on the pass gates of the SRAM cells, turning them off strongly. However, too negative a gate-to-source voltage will actually increase the leakage. The increase in leakage is due to a combination of gate leakage and Gate-Induced-Drain-Leakage (GIDL), both of which increase with increasing negative gate-to-source voltage on the pass gates in the SRAM array. This effectively limits how much SRAM standby power can be reduced by raising Vss-array.
SUMMARY OF THE INVENTION
An SRAM array, with improved leakage in standby, raises the wordline driver lower supply voltage when raising the array lower supply voltage in standby. When the SRAM array is in active mode, a source voltage is provided to the SRAM array lower supply node and to the wordline driver lower supply node. When the SRAM array is in standby mode, a voltage offset is provided between the source voltage and both the SRAM array lower supply node and the wordline driver lower supply node.
REFERENCES:
patent: 5274601 (1993-12-01), Kawahara et al.
patent: 5274788 (1993-12-01), Koike
patent: 5361227 (1994-11-01), Tanaka et al.
patent: 5634105 (1997-05-01), Mizuno
patent: 5771190 (1998-06-01), Okamura
patent: 5943273 (1999-08-01), Hidaka et al.
patent: 6198671 (2001-03-01), Aoyama et al.
Brady III W. James
Phan Trong
Stewart Alan K.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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