Memory array and method for writing data to memory

Static information storage and retrieval – Systems using particular element – Flip-flop

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Details

36518904, 36523005, G11C 1100

Patent

active

060469307

ABSTRACT:
A column (10) of a memory array includes a plurality of memory cells (11, 12) each having first and second independent access ports (T1, T2) and a cross-coupled memory latch (20). The first access port (T1) of each memory cell (11, 12) connects a first node (21) of the latch (20) to a first bit line (14), while the second access port (T2) of each memory cell connects a second node (22) of the latch (20) to a second bit line (15). A clearing arrangement (T7) is connected to the second bit line (15) for selectively coupling the second bit line to ground. A write driver is connected to the first bit line (14) for writing data to the memory cells (11, 12) in the form of single-ended signals. A memory cell is placed in a preset condition by simultaneously coupling the second node (22) to the second bit line (15) through the second access port (T2) and coupling the second bit line to ground through the clearing arrangement (T7). Once in the preset condition, data may be written to the cell by coupling the first bit line (14) to the first node (21) through the first access port (T1) and driving data to the first bit line.

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