Memory array addressing circuitry

Details Memory array addressing circuitry Memory array addressing circuitry

1980-04-18

1984-06-05

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Signals

365230, G11C 1300

Patent

active

044532369

ABSTRACT:
An integrated circuit comprises a memory array containing a plurality of memory cells arranged in a matrix shape having rows and columns, and memory array addressing circuitry for addressing such array in accordance with addressing signals. Said addressing circuitry comprises a number of gates responsive to addressing signals for addressing the array. Only one of the number of gates has a control signal applied thereto which places the memory array in such a condition that none of the memory cells is selected for addressing purposes, and the remaining gates do not have a control signal applied even under the same situation, wherein none of the memory cells is selected for addressing purposes. The gates comprise an AND gate, an NAND gate, an NOR gate or the like.

REFERENCES:
patent: 3471838 (1969-10-01), Ricketts et al.
patent: 3969706 (1976-07-01), Probsting
patent: 4037098 (1977-08-01), Horninger

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