Memory array

Static information storage and retrieval – Floating gate

Reexamination Certificate

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Details

C365S185050, C365S185260

Reexamination Certificate

active

07072210

ABSTRACT:
A memory array including a plurality of word lines, a plurality of first source/drain lines, a plurality of second source/drain lines, and a plurality of memory units. Each memory unit includes a gate electrode coupled to one of the word lines, a first source/drain region coupled to one of the first source/drain lines or first bit lines, a second source/drain region coupled to one of the second source/drain lines or second bit lines, a first spacer between the first source/drain region and the gate electrode to store electrons or electric charges, and a second spacer between the second source/drain region and the gate electrode to store electrons or electric charges.

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patent: 6524913 (2003-02-01), Lin et al.
patent: 6545915 (2003-04-01), Ohtani et al.
patent: 6577531 (2003-06-01), Kato
patent: 6788601 (2004-09-01), Takano et al.
patent: 6855608 (2005-02-01), Ramsbey et al.
patent: 6903968 (2005-06-01), Jeng
patent: 2004/0023440 (2004-02-01), Ito et al.
patent: 2004/0119112 (2004-06-01), Lojek
patent: 406302830 (1993-04-01), None

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