Memory array

Static information storage and retrieval – Systems using particular element – Flip-flop

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Details

307291, 365154, G11C 1140

Patent

active

041225422

ABSTRACT:
An integrated circuit memory array having a plurality of memory cells including two cross-coupled transistors of one conductivity type, load transistors of the other conductivity type, and a bit line, connected to the base region of one of the cross-coupled transistors through a bit line transistor. The array features a common node, directly interconnecting all of the base regions of the load transistors and the emitter regions of the cross-coupled transistors, for each of the memory cells; and a row selection line connected to the emitter regions of the load transistors in an associated row of memory cells.

REFERENCES:
patent: 3655999 (1972-04-01), Wiedmann
patent: 3745540 (1973-07-01), Taniguchi et al.
patent: 3801967 (1974-04-01), Berger et al.
Wiedmann, Random Access Memory Cell, IBM Technical Disclosure Bulletin, 11/71, vol. 14, No. 6, pp. 1721-1722.
Wiedmann, High-Density Static Bipolar Memory, 1973, IEEE International Solid-State Circuits Conference, 2/14/73, pp. 56-57.

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