Memory arrangement in a computer system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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C714S054000

Reexamination Certificate

active

10902160

ABSTRACT:
A memory arrangement in a computer system can have at least one memory module with semiconductor components, which are arranged on the memory module, can be operated in parallel and are additionally connected to one another via a serial line. The memory arrangement can have an interface bus for driving the semiconductor components on a module-specific basis, and an interface, which is driven by a memory controller assigned to the memory module via the interface bus and accesses the semiconductor components via the serial line. During normal operation, it is possible to test and adjust the semiconductor components in proximity to the application and on a chip-specific basis via the interface.

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Jarwala, N.; “Designing “Dual Personality” IEEE 1149.1 Compliant Multi-Chip Modules”; International Test Conference 1994; pp. 446-455.

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