Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2002-02-19
2008-08-26
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S167000, C711S103000, C711S104000, C710S052000
Reexamination Certificate
active
07418566
ABSTRACT:
A memory arrangement is provided, which has a programmable memory and a first buffer memory associated with the programmable memory, to which buffer memory, in the case of a command access, at least one command following the accessed command is written. A second buffer memory may also be provided, to which buffer memory, in the case of a data access, at least one datum following the accessed datum is written. Also provided is a method for reading from a memory arrangement during program execution, wherein presence of a command access or a data access recognized, and a command following the accessed command is written to a first buffer memory and a datum following the accessed datum is written to a second buffer memory. Thus, in this manner, a separate buffer memory is described for data accesses, and thus the content of the buffer for command accesses is not overwritten or destroyed when data accesses occur during the program execution.
REFERENCES:
patent: 6161162 (2000-12-01), DeRoo et al.
patent: 6490666 (2002-12-01), Cabrera et al.
patent: 6567335 (2003-05-01), Norman et al.
Aue Axel
Graf Jens
Thomas Martin
Kenyon & Kenyon LLP
Nguyen Than
Robert & Bosch GmbH
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