Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2005-12-23
2008-10-28
Nguyen, Viet Q (Department: 2827)
Static information storage and retrieval
Read/write circuit
Signals
C365S191000, C365S193000, C365S189080, C365S076000, C327S147000, C327S153000, C711S167000
Reexamination Certificate
active
07443742
ABSTRACT:
A memory arrangement for processing data comprises a memory, an interface operatively coupled to the memory, a DLL circuit and at least one register device comprising a data input and a clock input. Read data is applied to the interface in response to a read access to the memory. An RDT clock signal, which is derived from an internal clock signal and is in synchronism with the read data, is permanently applied to the interface. The DLL circuit provides a delayed clock signal defining a optimum sampling time for the read data as a signal obtained by comparing the internal clock signal with the RDT clock signal and shifting the obtained signal if at least one of a set-up time or a hold time is violated. The data input of said at least one register device is connected to the interface and the delayed clock signal is applied to the clock input of the at least one register device in order to sample the read data.
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Infineon - Technologies AG
Maginot Moore & Beck
Nguyen Viet Q
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