Computer graphics processing and selective visual display system – Computer graphics display memory system – Frame buffer
Reexamination Certificate
1999-06-25
2002-12-03
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Frame buffer
C345S560000, C345S660000
Reexamination Certificate
active
06489964
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a memory arrangement comprising a frame buffer unit comprising memory equipment clocked by a memory clock, and a scaler unit.
2. Description of the Related Art
The most suitable random access memory (RAM) device for a frame buffer is Synchronous Dynamic RAM (SDRAM). This type of memory is used in large quantities for graphics controllers. The conventional SDRAM devices are single port devices. This means that time multiplexing is required if a continuous stream of data needs to be written into and read from the SDRAM. For digital video, normally 8 bits per color are used. The typical data width of commercially available SDRAM devices is 16 bits. Furthermore, SDRAM devices are available that can run on the sampling frequency of the incoming video. Furthermore, the memory size of these devices is large enough to store the video samples of one field for one color. With these memories, the frame buffer can be realized using three SDRAM devices, where each color requires one SDRAM device. To obtain a high data rate, the SDRAM needs to be addressed in a burst mode. The burst length is in general a power of 2 (e.g., 2, 4, 8, 16, etc.). This means that at the input and output of the frame buffer, first-in, first-out (FIFO) memories are required. During a burst, two samples are read from or written into the memory in parallel. This means that at the input and output, a multiplexer is required.
For simplicity, it will be assumed that half of the available time is used to write incoming data into the SDRAM where the other half is used to read data from the SDRAM. Furthermore, the input FIFO and output FIFO should be as small as possible which means that a read burst should interleave with a write burst. In order to address the memory correctly, some addressing overhead is required. This means that for a burst transfer of N samples, &Dgr;N additional clock cycles are required for each burst. This means that the data throughput of the SDRAM needs to be larger than the sum of the input and output data throughput. To solve this problem in the frame buffer itself, the following solutions are applicable: increase the number of SDRAMs, use large input and output FIFOs, or increase the clock frequency. The first solution is not attractive because this will increase the costs and pin count of the frame buffer. The second solution works as follows. Since only the active video data needs to be stored into the frame buffer, no data is written during horizontal blanking time. When large input and output FIFOs are used, the horizontal blanking time can compensate for the addressing overhead. As mentioned in the introduction, it is desired to use a gate array design for the frame buffer controller. In a gate array, it is not realistic to implement this kind of large memories. The third solution is increasing the clock frequency of the SDRAM. For simplicity, it was assumed that read bursts are interleaved with write bursts. In that case the memory clock frequency should satisfy
fm
=
max
(
Δ
N
+
N
N
·
fin
,
Δ
N
+
N
N
·
fout
)
In this case, it can be computed that it is sufficient to use input and output FIFOs that can store 2N samples. A disadvantage of this system is that this concept requires three different clocks (viz. an input clock fin, a frame buffer memory clock fm, and an output clock fout) which makes the design of such a frame buffer more difficult. Furthermore, it is less attractive from an integration point of view. Especially when these clocks are generated by a PLL, additional circuitry is necessary.
SUMMARY OF THE INVENTION
It is, inter alia, an object of the invention to allow the frame buffer unit to operate with less than three different clocks. To this end, a first aspect of the invention provides a memory arrangement having a scaler unit and a frame buffer unit. Another aspect of the invention provides; a display apparatus including such a memory arrangement. Further aspects of the invention provide; ICs and frame buffer unit ICs which are preferably applied in a memory arrangement in accordance with the present invention.
In a memory arrangement comprising a frame buffer unit comprising memory equipment clocked by a memory clock, and a scaler unit, in accordance with a primary aspect of the invention, the scaler unit comprises at least one line memory for converting a continuous input data stream into a frame buffer data stream in which samples of two successive data bursts of N samples are situated N+&Dgr;N samples apart from each other, and/or for converting such a frame buffer data stream into a continuous output data stream.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
REFERENCES:
patent: 5142637 (1992-08-01), Harlin et al.
patent: 5257103 (1993-10-01), Vogeley et al.
patent: 5615376 (1997-03-01), Ranganathan
patent: 6189064 (2001-02-01), MacInnis et al.
patent: 9734285 (1997-09-01), None
“Frame Buffer Wars: New Directions in PC Graphics”, by David Kocsis, EDN Design Feature, May 23, 1996, pp. 121-128.
Gathman Laurie E.
Tung Kee M.
LandOfFree
Memory arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory arrangement will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2996388