Memory architecture with sub-arrays

Details Memory architecture with sub-arrays Memory architecture with sub-arrays

1985-07-01

1987-10-06

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

365203, G11C 1300

Patent

active

046987886

ABSTRACT:
A static RAM has a plurality of sub-arrays arranged in rows and columns, each sub-array having word lines running the length of the sub-array in a top to bottom direction, and having bit lines running the width of the sub-array in a left to right direction, and having a word line driver for enabling a selected word line in response to receiving a row select signal corresponding to the selected word line; a global row decoder for providing the row select signals as determined by row address signals; a first plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a first of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; a second plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a second of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; and a plurality of sense amplifiers for sensing the output of the first and second column decoders. The static RAM has an architecture characterized by the memory having a top side, a bottom side, a left side, and a right side; the rows of sub-arrays running from left to right, and sequentially numbered from left to right with the first column of sub-arrays being nearest the top side; the columns of sub-arrays running from top to bottom, and sequentially numbered from top to bottom with the first row sub-arrays being nearest the left side; and the plurality of sense amplifiers being interposed in the rows of sub-arrays and located between the columns of sub-arrays.

REFERENCES:
patent: 4239993 (1980-12-01), McAlexander, III et al.
patent: 4366559 (1982-12-01), Misaizu et al.
patent: 4528646 (1985-07-01), Ochii et al.
1982 IEEE ISCC Digest Technical Papers, Session XVIII: Static RAMS, A 64Kb CMOS RAM, Konishi et al., Feb. 12, 1982, pp. 258, 259 and 333.
1982 IEEE ISCC Digest Technical Papers, Session XVIII: Static RAMS, A 15nW Standby Power 64Kb CMOS RAM, Ochii et al., pp. 260, 261, 334.

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