Memory architecture with memory cell groups

Details Memory architecture with memory cell groups Memory architecture with memory cell groups

2002-09-19

2004-04-20

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S071000, C257S296000, C257S298000, C438S003000

Reexamination Certificate

active

06724026

ABSTRACT:

BACKGROUND OF INVENTION
Ferroelectric metal oxide ceramic materials such as lead zirconate titanate (PZT) have been investigated for use in ferroelectric semiconductor memory devices. The ferroelectric material is located between two electrodes to form a ferroelectric capacitor for storage of information. Ferroelectric capacitor uses the hysteresis polarization characteristic of the ferroelectric material for storing information. The logic value stored in a ferroelectric memory cell depends on the polarization direction of the ferroelectric capacitor. To change the polarization direction of the capacitor, a voltage which is greater than the switching voltage (coercive voltage) needs to be applied across its electrodes. The polarization of the capacitor depends on the polarity of the voltage applied. An advantage of the ferroelectric capacitor is that it retains its polarization state after power is removed, resulting in a non-volatile memory cell.
Referring to
FIG. 1
, a plurality of memory cells
105
are shown. The memory cells, each with a transistor
130
coupled to a capacitor
140
in parallel, are coupled in series to form a group
102
. Series memory architectures are described in, for example, Takashima et al., “High Density Chain Ferroelectric Random Access Memory (chain FRAM)”. IEEEJrnl. of Solid State Circuits, vol.33, pp.787-792, May 1998, which is herein incorporated by reference for all purposes. The gates of the cell transistors can be gate conductors which are coupled to or serve as wordlines. A selection transistor
138
is provided to selectively couple one end
109
of the group to a bitline
150
. A plateline
180
is coupled to the other end
108
of the group. Numerous groups are interconnected via wordlines to form a memory block. Sense amplifiers are coupled to the bitlines to facilitate access to the memory cells.
FIG. 2
shows a conventional cross-section of a memory group
202
. The transistors
230
of the memory cells
205
are formed on a substrate
210
. Adjacent cell transistors shared a common diffusion region. The capacitors
240
of the memory group are arranged into pairs. The capacitors of a capacitor pair share a common bottom electrode
241
. The bottom electrodes are coupled to the cell transistors via active area bottom electrode (AABE) plugs
285
. The top electrode
242
of a capacitor from a capacitor pair is coupled to the top electrode of a capacitor of an adjacent pair and cell transistors. The top capacitor electrodes are coupled to the cell transistors via active area top electrode (AATE) plugs
286
. Between the electrodes is a ferroelectric layer
243
. A barrier layer
263
, such as iridium, is located between the electrode and the AABE plug. At a first end
209
of the group is a selection transistor (not shown) having one diffusion region coupled to a bitline. The other diffusion region is a common diffusion region with the cell transistor on the end of the group. A plateline is coupled to a second end
208
of the group.
Conventionally, the formation of the capacitors requires two etch steps. Specifically, the barrier and bottom electrode layers are deposited and patterned to provide a common bottom electrode for each capacitor pair. Then the ferroelectric and top electrode layers are deposited and patterned, completing the processing of the capacitors. The need for two process steps to form the capacitors undesirably increases process complexity, costs, and raw process time. Furthermore, an overetch is performed to ensure that the ferroelectric layer is completely patterned. This overetch may result in the thinning of the barrier layer in regions
274
between the capacitors of a capacitor pair. This may compromise the barrier layer, resulting in the AABE plugs
285
located below region
274
being oxidized. Also, conventional techniques for forming the capacitors in a series architecture requires the bottom electrode to overlap the top electrodes. This undesirably increases cell size (e.g., area penalty).
From the foregoing discussion, it is desirable to provide an improved memory group which avoids the disadvantages of conventional series memory architectures.
SUMMARY OF INVENTION
The invention relates to memory cells configured in a series architecture. The memory group includes at least one pair of memory cells. A memory cell comprises a capacitor having a dielectric layer between first and second electrodes and a cell transistor with first and second diffusion region, wherein the second diffusion regions of the cell transistor is a common diffusion region shared between the cell transistors of the memory cell pair.
The bottom electrodes of the pair of capacitors are coupled to the second diffusion region. In one embodiment, a bottom electrode plug is provided for each capacitor, coupling the bottom electrode to the second diffusion region. Top electrodes are coupled to first diffusion region of the respective cell transistor. In one embodiment, the memory cells are ferroelectric memory cells having a ferroelectric layer between first and second electrodes.


REFERENCES:
patent: 5936272 (1999-08-01), Lee
patent: 6500677 (2002-12-01), Bergmann et al.
patent: 6521929 (2003-02-01), Ozaki

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