Computer graphics processing and selective visual display system – Computer graphics display memory system – Memory partitioning
Reexamination Certificate
1999-06-10
2002-08-13
Chauhan, Ulka (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Memory partitioning
C345S537000, C345S557000
Reexamination Certificate
active
06433786
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory architecture for a video graphics environment. More particularly, the present invention relates to a memory architecture that includes a dynamic random access memory (DRAM) and a dual ported static random access memory (SRAM) coupled by a page wide bus. This memory architecture improves the efficiency of employing a DRAM as a video memory in a video graphics environment.
2. The Prior Art
The on screen resolution of the video provided by video graphics cards has been increasing in performance at a tremendous rate. Much of this increase has been based on the improvements of the video graphics controller in the video graphics card. Unfortunately, the access time required by the memory devices, usually DRAMS, used by the video graphics controllers have not kept pace with the increased performance of video graphics controllers. Presently, the gap between video graphics controller performance and DRAM access time continues to widen. There are several reasons for this widening gap.
A DRAM is an integrated circuit wherein typically an array of memory cells are arranged in rows and columns. For example, a 4 megabyte DRAM has memory cells arranged in a square matrix of 2048 rows by 2048 columns. Each of the memory cells stores a bit of information by the presence or absence of an electrical charge on a capacitor. In a DRAM, “refresh” circuitry is provided for restoring to full charge a capacitor that has been partially discharged.
In many applications, DRAMs, known as page mode DRAMs have been employed wherein the requestor of the data can use all of the data in an entire page at one time. When the data is sought by data requestors in the video graphics controller, however, this is typically not the case. In a video graphics environment, the memory sequencer receives data I/O requests from various data requesters, determines the priority of data I/O access among the data requesters, and obtains the data from the DRAM accordingly. Typically, each of the requesters only a few bytes of data at a time. For example, a first data requestor will want a few bytes of data, and then another data requestor will want a few bytes of data, and then a third requestor will want a few bytes of data,etc. As a result, even though an entire page can be read from the DRAM in page mode, only a few bytes of data will be used from each memory cycle.
One approach to utilize the page mode capabilities of a DRAM in a video graphics environment is to read the DRAM contents into a memory cache. As is well understood by those of ordinary skill in the art, a cache memory is organized and addressed with tags to identify the portions of the DRAM memory which the cache memory represents. When the requested data is within the cache memory, this is called a cache hit. When the data sought is not within the cache memory, this is called a cache miss. When a cache miss is made, the requested data must then be retrieved from the main DRAM memory. Different organizational approaches of the cache memory include direct mapped cache, full-associative cache, and set associative cache. The particular organization of the cache memory and the tags employed depends largely on system for which the cache memory is being employed.
The cache memory is employed to improve the efficiency in the use of the page mode DRAM in a video graphics environment on the assumption that despite the fact that the data requestors may request only a few bytes of data at a time, the data in the cache memory will be the few bytes of data in the main memory that is more frequently accessed than other data. Employing a cache memory, however, has the drawbacks of overhead of cache organization, addressing tags, and a slow memory retrieve from the main DRAM memory when there is a cache memory miss.
Further, employing a cache memory in a video graphics environment to improve the efficiency in the use of a page mode DRAM does not contemplate or appreciate that the bytes of data requested by some the data requesters are not simply the same bytes of data being used repeatedly, but that the linear order of the bytes being used are essentially predictable. Because of this linear predictability, there is room for improving the efficiency of using a page mode DRAM in a video graphics environment by taking into account the linear predictability of the data being used by the data requestors.
SUMMARY
A memory architecture for a video graphics controller includes a dynamic random access memory (DRAM), a static random access memory (SRAM) and a bus. The DRAM includes a data port, an address decoder that can receive an address to select a memory location in the DRAM and a command instruction bus that can receive instructions for data transfer. The SRAM includes a first data port to transfer data with the DRAM, a second data port to transfer data with other than the DRAM, a first address decoder that can receive an address to select a memory location in the SRAM for data transfer with the DRAM, a first read/write input that can receive a signal for data transfer with the DRAM, a second address decoder that can receive an address to select a memory location in a page of the SRAM to transfer data with other than the DRAM and a second read/write input that can receive a signal for data transfer from other than the DRAM. The bus is coupled between the data port of the DRAM and the first data port of the SRAM for data transfer between the DRAM and the SRAM.
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Chauhan Ulka
Intel Corporation
Schaub John P.
Thelen Reid & Priest LLP
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