Memory architecture for micromirror cell

Details Memory architecture for micromirror cell Memory architecture for micromirror cell

2001-12-28

2004-08-10

Yoha, Connie C. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S237000, C365S106000

Reexamination Certificate

active

06775174

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to micromirror spatial light modulators and more specifically to a new one transistor, one capacitor memory cell for these devices.
2. Description of the Related Art
Early micromirror spatial light modulators, such as the DMD™ from Texas Instruments Incorporated, used two transistor (2T) DRAM underlying memory cells as shown in FIG.
1
. These were bi-directional devices where the reflective mirror
20
(known as the beam) rotated ±10°. The device was comprised of the beam
20
, two address electrodes
12
and
13
, two address transistors
10
and
30
, and two landing pads
11
and
14
. When data was read into these devices, it was stored on substrate depletion capacitors
15
and
16
located at the address nodes of transistors
30
and
10
, respectively. In order to keep the address voltage applied to the address electrodes
12
and
13
at reasonable levels (0 to 5V), the beam
20
was biased at −|V
b
|, as shown. With a beam bias of −16 volts, the micromirror would operate in the bistable mode with 0V and +5V address voltages. In operation, the electrode at 0V would have a potential between the beam and electrode of 16−0=16V (magnitude only) while the electrode at +5V would have a potential of 16−5=11V, so the beam would tilt towards the 0V electrode side. Notice that in these devices there are landing pads
11
and
14
at the same electrical potential as the beam
20
on which the beam
20
touches down and lands. The geometry of the device is such that when the mirror lands it is tilted ±10°.
The problem with these early 2T DRAM micromirror spatial modulators, however, was that the substrate storage capacitors
15
and
16
were extremely sensitive to light generated carriers in the substrate which would recombine with the stored charge (electrons) and discharge the capacitor. At the bright illumination levels found in projection displays, the devices could not hold the charge which had been read in long enough to address the mirrors, making them unusable in most practical display applications.
This problem was initially addressed by going to a 6T (six transistor) SRAM memory cell which acted as a flip-flop and latched the data in place until it was reset. These devices worked quite well in bright illumination environments, but they were more complicated to manufacture with the additional transistors and this led to yield and size problems at the chip level.
In an attempt to get back to the simpler DRAM memory cell, the problems were addressed in two primary areas; (1) the number of transistors and (2) the charge retention problem. First, the problem relating to the number of transistors was addressed by the 1T (one transistor) driven beam approach shown in
FIGS. 2
a
and
2
b
. In this case, the address signal &phgr;
a
is placed on the beam
20
rather than on the electrodes and is supplied by transistor
50
. Then differential signals &phgr;
b(+)
and &phgr;
b(−)
are applied to electrodes
51
and
52
, where:
&phgr;
a
=+|V
a
|,
&phgr;
b(−)
=−|V
b
|
and
&phgr;
b(+)
=+|V
b
|+|V
a
|.
Landing electrodes
11
and
14
in the earlier 2T DRAM design are replaced by oxide (insulated) landing pads
53
and
54
in this case since the beam and landing sites are at different potentials. In a typical operation, the beam
20
waveform is &phgr;
a
=+|V
a
|, having magnitude of 5 volts from 0V to +5V. In order to achieve bi-directional operation the negative bias electrode
51
voltage is &phgr;
b(−)
=−|V
b
|=−15V and the positive bias electrode
52
is &phgr;
b(+)
=+|V
b
|+|V
a
|=+20V. When the beam
20
is addressed to 0V, there is a +15 volt potential difference between beam
20
and negative vias electrode
51
and a −20 volt potential difference between the beam
20
and positive bias electrode
52
(magnitudes only). Since the potential difference between the beam
20
and positive bias electrode
52
is 5 volts greater, this larger electric field will cause the beam
20
(mirror) to tilt 10° in the positive direction. Similarly, when the beam
20
is addressed to +5V there is a +20 volt potential difference between beam
20
and the negative bias electrode
51
and only a −15 volt difference between the beam
20
and positive bias electrode
52
, so the beam will rotate −10°, in the negative direction.
FIG. 2
b
shows the typical response for a bi-stable micromirror pixel which is digitally deflected between its quiescent state (0° deflection) and its tilted state (approximately ±10° deflection). As shown, 90% of the optical response
200
occurs within 12 &mgr;Sec from the leading edge of the address pulse
210
. In operation, it is necessary for the device to be loaded and the mirrors addressed multiple times during the 16.7 mSec frame time, depending on the number of digitized bits utilized. Therefore, when loading the most significant bit, it is necessary to hold the charge in the memory cell for approximately 8.4 msec. Both the 2T and 1T memory cell approaches are described in U.S. Pat. No. 5,142,405.
The charge retention problem has been addressed in a number of ways, one using a metal light shield that requires additional metal layers which negatively impact fabrication yield and cost of the micromirror chips. Another approach uses a guardring DRAM cell to help prevent recombination of photo-generated carriers. This technique is discussed below and in an earlier patent application Ser. No. 09/468,595.
FIG. 3
, which shows a cross-section side view of a memory cell
300
, illustrates the problem of photo-carrier recombination. Here the memory cell
300
is fabricated on a P-doped semiconductor (typically silicon) substrate
316
. The upper plate
312
of the storage capacitor and the gate
314
of the transistor are formed with a deposited polycrystalline material. The gate of the transistor is connected to the write line
308
. Vias
318
are opened through an oxide layer
320
to allow connection of the address line
306
to the source of the transistor and connection of the transistor drain to the polysilicon capacitor
312
to form address node
310
.
In operation, photo-carriers (photo-generated electrical charges) are formed when photons
326
strike the semiconductor substrate. The energy of the photon
326
frees an electron from an atom to form an electron-hole pair which may drift or diffuse toward the address node
310
where it can recombine. If enough electrons reach the address node
310
, the charge on the capacitor may not be sufficient to assure proper deflection of the micromirror mirror.
A solution to the photo-carrier recombination problem discussed above is to use an active collection region to form the bottom plate of the storage capacitor and act as a guardring that recombines photo-carriers before they reach the address node, located between the transistor and capacitor of the memory cell.
FIG. 4
a
shows the guardring memory cell
300
comprising a transistor
302
(comprising a gate
314
connected to the write line
308
and an address line
306
), an address node
310
, and a capacitor
304
(comprising an upper plate
312
and an active lower plate or region
326
which is connected to a positive bias).
FIG. 4
b
is a cross-section side view of the DRAM memory cell
300
of
FIG. 3
with n-well guardring
330
added around the negative plate of the capacitor
304
. This approach, comprised of transistor
302
and ring capacitor
304
, effectively adds the n-well guardring
330
to the basic memory cell shown in FIG.
3
. In this case, the lower plate of the capacitor
304
is positively biased by means of its connection
328
to a positive supply voltage. In operation, the n-well
330
ser

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