Memory architecture for increased speed and reduced power...

Details Memory architecture for increased speed and reduced power... Memory architecture for increased speed and reduced power...

2006-04-25

2006-04-25

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S063000, C365S156000

Reexamination Certificate

active

07035132

ABSTRACT:
An improved multi-wordline memory architecture providing decreased bitline coupling to increase speed and reduce power consumption including an interleaving arrangement for connecting adjacent bitcells to different wordlines, coupled to a multiplexing arrangement for sharing bitlines of adjacent bitcells.

REFERENCES:
patent: 5519655 (1996-05-01), Greenberg
patent: 5708620 (1998-01-01), Jeong
patent: 5828594 (1998-10-01), Fujii
patent: 5917744 (1999-06-01), Kirihata et al.
patent: 6160730 (2000-12-01), Tooher

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