Memory architecture for flexible reading management, particularl

Details Memory architecture for flexible reading management, particularl Memory architecture for flexible reading management, particularl

1997-04-24

1999-06-29

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

365233, 3652335, G11C 702

Patent

active

059177683

ABSTRACT:
A memory device for flexible reading management, particularly for non-volatile memories, including at least one memory matrix; at least one sense amplifier for capturing data from the at least one memory matrix; at least one output buffer for providing the data as an output, connected to the sense amplifier by an internal bus; at least one row decoder for selecting the word lines of the memory matrix; a memory read address transition detection circuit adapted to produce an address transition signal; a circuit for enabling/disabling the read circuits; a circuit for enabling a reading process, adapted to enable the reading process only after the minimum functionality levels of the memory cells involved in the reading process and of all the connected read circuits have been reached; a propagation reproduction circuit; a network for equalizing and correlating the reading with respect to the characteristics of the circuits, signal propagations, and conductivity of the memory cells; a reading cycle end circuit adapted to determine the end of the reading process; and a circuit for synchronized and time-limited loading of the data in the at least one output buffer.

REFERENCES:
patent: 5371716 (1994-12-01), Yamanaka
patent: 5592434 (1997-01-01), Iwamoto et al.
patent: 5694369 (1997-12-01), Abe

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