Memory architecture dependent program mapping

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711118, 711133, 711158, G06F 1200

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active

059639725

ABSTRACT:
In a computer implemented method, instructions of a program are mapped into a cache memory of a computer system. The cache memory is partitioned into a plurality fixed size lines for the convenience of accessing the instructions. Each block is assigned a different identification, for example a unique color. The program is partitioned into a plurality of instruction units, for example procedures or basic blocks. A flow graph is generated for the program. In the graph, nodes represent the instructions units, and edges directly connect nodes that have an execution relationship. Instruction units of directly connected nodes are mapped into blocks having different identifications or colors. An unavailable-set of identifications is maintained for each node. The unavailability-set of a particular node includes the identifications of blocks mapping instruction units directly connected to the particular node and which should not be used for the particular procedure in order to minimize cache conflicts during execution of the program.

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Hwu, Wen-mel W. And Chang, Pohua P.; Coordinated Science Laboratory, Unversity of Illinois, 1989; Achieving HIgh Instruction Cache Performance With An Optimizing Compiler; pp. 242-251.
Torrellas, Josep and Xia, Chun and Daigle, Russell; Center for Supercomputing Research and Development; Optimizing Instruction Cache Performance for Operating System Intensive Workloads.
Hashemi, Amir H. And Kaeli, David R. and Calder, Brad; WRL Research Report 96/3, Oct. 1996; Efficient Procedure Mapping using Cache Line Coloring.

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