Static information storage and retrieval – Read/write circuit – Parallel read/write
Reexamination Certificate
2000-03-24
2001-05-29
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Parallel read/write
C365S189040, C365S221000
Reexamination Certificate
active
06240031
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to FIFO memories generally and, more particularly, to flag generation and cascadability of memories at double data rate (DDR) frequencies.
BACKGROUND OF THE INVENTION
Flag generation and cascadability of DDR first-in first-out (FIFO) memories are factors limiting the maximum operating frequency. One conventional approach is to implement an external ping-pong logic and use two slower FIFOs. Referring to
FIG. 1
, an example of a circuit
10
illustrating a conventional FIFO is shown. Two or more conventional FIFOs
10
a
-
10
n
, when implemented in parallel, illustrate such an external ping-pong logic approach. The FIFO
10
has an input
12
that receives an input data signal DATA_IN <36:0> and an output
14
that presents an output data signal DATA_OUT <36:0>. The circuit
10
also has an input
16
that receives a read enable signal RENABLE and an input
18
that receives a write enable signal WENABLE. The circuit
10
also has an output
20
that presents an empty flag EF and an output
22
that presents a full flag FF. The inputs to the FIFOs
10
a
-
10
n
need to be connected in parallel and the outputs ping-pong every cycle, which results in (i) frequency degradation and/or (ii) the requirement of more board space.
Referring to
FIG. 2
, a timing diagram illustrating the operation of the circuit of
FIG. 1
is shown. A time Tf is shown as the time between a rising edge of the signal CLK and the enabling of the signal FLAG. Time Tens is equal to the difference between the time that the signal FLAG is enabled and the next rising edge of the signal CLK. As a result, the cycle time Tcycle is generally equal to the time Tf plus the time Tens. An example of a 100 Mhz signal CLK, the signal Tcycle is equal to 8 ns (e.g., Tf)+2 ns (e.g., Tens), for a total cycle time of lons.
Another conventional technique for implementing DDR FIFOs is to implement logic by using a slower and wider FIFO. Such an approach has the disadvantages of (i) being difficult to implement bus matching, (ii) having latency of at least two words, (iii) not implementing an odd word read out and/or (iv) consuming more board space.
Referring to
FIG. 3
, a circuit
30
illustrating a conventional width cascading architecture is shown. The circuit
30
has the disadvantage of being difficult to implement with bus matching. The circuit
30
alternately writes a first word of the signal DATA_IN to a FIFO
32
and a second word to a FIFO
34
. The circuit
30
also alternately reads a first word from the FIFO
32
and the FIFO
34
. The circuit
30
has the disadvantages of (i) being difficult to route the DATA_OUT on the board, (ii) having frequency of operation that is lower because of the loading on DATA_OUT and (iii) crowbar issues.
Referring to
FIG. 4
, an example of a circuit
70
implementing a conventional cascading (depth expansion) architecture is shown. The signal DATA_IN is presented through a FIFO
72
, a FIFO
74
and a FIFO
76
. The circuit
70
has the disadvantage of high latency through each of the FIFOs
72
,
74
and
76
.
SUMMARY OF THE INVENTION
One aspect of the present invention concerns an apparatus comprising a first memory and a second memory. The first memory may be configured read and write words from a data stream comprising a plurality of words in response to (i) a first read enable signal and (ii) a first write enable signal. The second memory may be configured to read and write words from the data stream in response to (i) a second read enable signal and (ii) a second write enable signal. The first and second memories may be configured to read and write alternate words of the data stream.
Another aspect of the present invention concerns an apparatus comprising a first memory, a second memory, a control circuit and a flag circuit. The first and second memories may each be configured to store data received from a first data input and present data to a first data output. The control circuit may be configured to control data stored in response to a write clock and control data presented in response to a read clock. The flag circuit may be configured to generate one or more composite flags in response to the first memory and the second memory.
The objects, features and advantages of the present invention include providing a memory architecture that may (i) double the operational clock frequency of existing FIFO technology by using internally slow divided clocks to drive internal odd and even FIFOs based on bus matching, (ii) improve performance that may be obtained by an automatic ping-pong of the data between internal odd and even FIFOs, which may essentially double the clock speed of the architecture, (iii) implement minimal logic that needs to operate at maximum frequency, (iv) allow at speed bus matching on a number of ports, (v) have two internal FIFOs working at half the frequency of an external clock, (vi) implement internal clock generation logic based on external bus matching mode, and/or (vii) be extended to multiple FIFOs with corresponding signals and flags to achieve an effective increase in the clock operating frequency.
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Mehrotra Rakesh
Narayana Pidugu L.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Nguyen Tan T.
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