Static information storage and retrieval – Addressing – Sync/clocking
Patent
1996-05-01
1997-06-17
Dinh, Son T.
Static information storage and retrieval
Addressing
Sync/clocking
365193, 36518902, 36518905, 36523002, G11C 800
Patent
active
056403615
ABSTRACT:
A memory architecture for providing wide data words up to the width of the address word, or wider than the address word, without requiring separate groups of electrical contacts for data and address. A dynamic random access memory arranged within a package comprises a memory array of dynamic memory cells and a first plurality of electrical contacts of the package each adapted for conducting both address signals and data signals. An address latch is coupled with the first plurality of electrical contacts for receiving the address signals therefrom during an address cycle and coupled with the memory array for transmitting the address signals thereto. A write latch is coupled with the electrical contacts for receiving the data signals therefrom during a data write cycle and coupled with the memory array for transmitting the data signals thereto.
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Dinh Son T.
Hewlett--Packard Company
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