Memory arbiter with intelligent page gathering logic

Details Memory arbiter with intelligent page gathering logic Memory arbiter with intelligent page gathering logic

2006-05-23

2006-05-23

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S151000, C711S154000, C710S240000

Reexamination Certificate

active

07051172

ABSTRACT:
Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

REFERENCES:
patent: 4365295 (1982-12-01), Katzman et al.
patent: 6006303 (1999-12-01), Barnaby et al.
patent: 6038631 (2000-03-01), Suzuki et al.
patent: 6681293 (2004-01-01), Solomon et al.

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