Memory arbiter with intelligent page gathering logic

Details Memory arbiter with intelligent page gathering logic Memory arbiter with intelligent page gathering logic

2001-12-28

2004-09-14

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S151000, C711S154000, C710S240000

Reexamination Certificate

active

06792516

ABSTRACT:

BACKGROUND
1. Field
The invention relates generally to computer systems, and in particular, to memory arbitration.
2. Background Information
Computer systems that employ a CPU often utilize a memory controller and a graphics controller. The memory controller controls access by the CPU and other agents to a system memory. The graphics controller controls the display of data provided by the CPU onto a display screen, such as a cathode ray tube (CRT), using a frame buffer. Both the system memory and the frame buffer are typically implemented using arrays of Dynamic Random Access Memory (DRAM). In some computer systems, the frame buffer and the system memory are unified into a single shared memory, known as a Unified Memory Architecture (UMA).
The time associated with accessing memory, retrieving the requested data from memory, and making the retrieved data available to a requesting agent is sometimes referred to as “latency.” Even those memory request that are generally more tolerant of a specific latency tend to be very sensitive to extreme variations in latency, even if these extremes occur infrequently. For example, once an isochronous stream begins, continuous data transfer becomes important and must be maintained. Therefore, the measure of quality in data transfer is often defined by the amount of data that can be lost without significantly affecting the audio or video quality. Lost data is directly related to extreme latency variations. Extreme latencies can cause data loss. If the data cannot be accessed in time, it is no longer useful.
Traditional computer systems have relied on various forms of priority-based memory arbitration, including priority, round-robin sequencing, time slice limits, high watermarks, etc., to determine the order in which an agent requesting access to memory should be serviced. While these kinds of arbitration schemes do function to reduce CPU memory latency, graphics memory traffic, such as graphics and AGP stream, are typically given lower priority, which can therefore cause a streaming agent to be “starved out” or sufficiently delayed in accessing memory, thereby resulting in lost data. Assigning higher priority to low priority graphics and AGP memory traffic results in an improvement of latency for the data, but doing so is at the expense of increased CPU memory latency. Accordingly, improvements are needed in the scheduling and processing of memory requests.


REFERENCES:
patent: 6006303 (1999-12-01), Barnaby et al.
patent: 6038631 (2000-03-01), Suzuki et al.
patent: 6058461 (2000-05-01), Lewchuk et al.
patent: 6298424 (2001-10-01), Lewchuk et al.
patent: 2003/0126380 (2003-07-01), Mastronarde et al.

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