Memory apparatus with random and sequential addressing

Details Memory apparatus with random and sequential addressing Memory apparatus with random and sequential addressing

1982-10-25

1986-04-08

Wolfe, John H.

Static information storage and retrieval

Addressing

365239, 364200, 364900, G11C 800, G11C 700

Patent

active

045817219

ABSTRACT:
A memory apparatus suitable for storing data for a high resolution bit mapped display includes large capacity (e.g. 64-k) semiconductor random access memory circuits in which to reduce the effective access time the circuits are operated and addressed in a repeating cycle including in succession reading from two or more addresses in sequence having the same row address component (i.e. in page mode), for example for the display, and writing into or reading from a randomly selected address.

REFERENCES:
patent: 3798617 (1974-03-01), Varadi et al.
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3962689 (1976-06-01), Brunson
patent: 4120048 (1978-10-01), Fuhrman

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