Static information storage and retrieval – Read/write circuit – Testing
Patent
1992-02-14
1994-02-22
LaRoche, Eugene R.
Static information storage and retrieval
Read/write circuit
Testing
371 402, G11C 700, G11C 2900
Patent
active
052894185
ABSTRACT:
The present invention provides a dedicated memory circuit which supports the generation of parity data in connection with the storing of data. This improved memory circuit allows the parity generation to be done remotely from the CPU while consuming less time. The memory array is provided with its data output being connected to combinational logic. Another input to combinational logic is for external data. The data already in the array and the new data are combined to the combinational logic, preferably an exclusive-or arrangement, to produce the parity data which is then returned to the memory array. A latch is provided between the exclusive-or logic and the memory array data lines to allow isolation of the data during the two cycles of the read out of the array and the right back to the array after the exclusive-or.
REFERENCES:
patent: 4654819 (1987-03-01), Stiffler et al.
patent: 4884271 (1989-11-01), Concha et al.
patent: 4958352 (1990-09-01), Noguchi et al.
patent: 4989210 (1991-01-01), Scheuneman et al.
patent: 4996690 (1991-02-01), George et al.
patent: 5012472 (1991-04-01), Arimoto et al.
patent: 5172339 (1992-12-01), Noguchi et al.
patent: 5191581 (1993-03-01), Woodbury et al.
Extended Systems, Inc.
Kessell Michael C.
LaRoche Eugene R.
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