Memory apparatus having multi-port architecture for...

Details Memory apparatus having multi-port architecture for... Memory apparatus having multi-port architecture for...

2007-01-30

2007-01-30

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S189030, C710S100000

Reexamination Certificate

active

10879274

ABSTRACT:
A memory apparatus for supporting a multiprocessor function enables data of different characteristics to be stored in one memory, thereby reducing the area of on the system board and decreasing delay margins on the data bus. The memory apparatus has an instruction memory unit arranged to be included in one memory chip and at least one data memory unit. The instruction memory unit includes cell array blocks having nonvolatile ferroelectric c stores instruction information required for operating a central processing unit of a system. The data memory unit is connected to the central processing unit by a data bus and is provided with cell array blocks having nonvolatile ferroelectric capacitors and stores execution data required for the execution of the instruction information.

REFERENCES:
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patent: 6240007 (2001-05-01), Kang
patent: 6272594 (2001-08-01), Gupta et al.
patent: 6363439 (2002-03-01), Battles et al.
patent: 2004/0210729 (2004-10-01), Horii et al.
patent: 06-075856 (1994-03-01), None

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