Static information storage and retrieval – Read/write circuit
Patent
1992-03-03
1993-03-09
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
36518904, 365200, G11C 1300
Patent
active
051930714
ABSTRACT:
Memory apparatus for simultaneously transferring data between corresponding memory cells of two RAMs is disclosed. The two memories are fabricated on a common integrated circuit chip substrate with the corresponding memory cells of the two memories positioned adjacent one another and interconnected through a pair of transfer transistors. The transfer transistors as well as the power supply to each memory cell are controllable to cause the simultaneous copying of the data from the cells of one RAM into the corresponding cells of the other RAM.
REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 3772658 (1973-11-01), Sarlo
patent: 4434502 (1984-02-01), Arakawa et al.
patent: 4449199 (1984-05-01), Daigle
patent: 4468727 (1984-08-01), Carrison et al.
patent: 4713756 (1987-12-01), Mackiewicz et al.
patent: 4864544 (1989-09-01), Spak et al.
patent: 4873665 (1989-10-01), Jiang et al.
patent: 4942575 (1990-07-01), Earnshaw et al.
Anselmo Robert A.
Umina Leonard J.
Digital Equipment Corporation
Fears Terrell W.
Maloney Denis G.
Myrick Ronald
Young Barry
LandOfFree
Memory apparatus for multiple processor systems does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory apparatus for multiple processor systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory apparatus for multiple processor systems will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-214447