Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-11-15
2010-12-28
Gu, Shawn X (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S103000, C711S104000, C711S119000, C711S143000, C711SE12017
Reexamination Certificate
active
07861040
ABSTRACT:
A memory apparatus including: a cache control section to control a cache memory for an auxiliary storage apparatus; a volatile memory; and a nonvolatile memory, wherein the cache memory for the auxiliary storage apparatus is configured to have a volatile cache memory provided in the volatile memory and a nonvolatile cache memory provided in the nonvolatile memory, and wherein the cache control section accesses the nonvolatile cache memory using a write back method.
REFERENCES:
patent: 5748985 (1998-05-01), Kanai
patent: 7-44982 (1995-02-01), None
patent: 07-121444 (1995-05-01), None
patent: 08-171515 (1996-07-01), None
patent: 11-203828 (1999-07-01), None
patent: 2002-7213 (2002-01-01), None
patent: 2004-005778 (2004-01-01), None
Japanese Office Action dated Jan. 22, 2009.
Eguchi Munetoshi
Ishikawa Tetsuya
Moromizato Nao
Nishimura Hiroyasu
Ogawa Tomoya
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Gu Shawn X
Konica Minolta Business Technologies Inc.
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