Memory apparatus, cache control method, and cache control...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S103000, C711S104000, C711S119000, C711S143000, C711SE12017

Reexamination Certificate

active

07861040

ABSTRACT:
A memory apparatus including: a cache control section to control a cache memory for an auxiliary storage apparatus; a volatile memory; and a nonvolatile memory, wherein the cache memory for the auxiliary storage apparatus is configured to have a volatile cache memory provided in the volatile memory and a nonvolatile cache memory provided in the nonvolatile memory, and wherein the cache control section accesses the nonvolatile cache memory using a write back method.

REFERENCES:
patent: 5748985 (1998-05-01), Kanai
patent: 7-44982 (1995-02-01), None
patent: 07-121444 (1995-05-01), None
patent: 08-171515 (1996-07-01), None
patent: 11-203828 (1999-07-01), None
patent: 2002-7213 (2002-01-01), None
patent: 2004-005778 (2004-01-01), None
Japanese Office Action dated Jan. 22, 2009.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Memory apparatus, cache control method, and cache control... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory apparatus, cache control method, and cache control..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory apparatus, cache control method, and cache control... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4211020

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.