Memory apparatus and memory control method

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

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711205, 39580034, 395555, G06F 1200

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active

059875739

ABSTRACT:
An empty block table is constructed by 64 words.times.8 bits and has 512 memory positions 000H(A0) to IFFH(A511) one-to-one corresponding to 512 blocks BL0 to BL511 within a flash memory FMi. Empty data [a] of 1 bit is stored to each memory position (Aj). This empty data has value "1" when a block BLj corresponding to this memory position (Aj) is in an empty state at present. The empty data also has value "0" when no block BLj corresponding to this memory position (Aj) is in the empty state at present (when data are included in this block).

REFERENCES:
patent: 4314333 (1982-02-01), Shibayama et al.
patent: 5524230 (1996-06-01), Sakaue et al.
patent: 5581503 (1996-12-01), Matsubara et al.
patent: 5611607 (1997-03-01), Okamoto et al.
patent: 5627783 (1997-05-01), Miyauchi
patent: 5678098 (1997-10-01), Ishihara et al.
patent: 5708603 (1998-01-01), Tanaka
patent: 5729720 (1998-03-01), Kau et al.

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