Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-09-18
2007-09-18
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S195000
Reexamination Certificate
active
10573460
ABSTRACT:
A memory chip includes a main memory cell; a row-wise redundant memory cell and a column-wise redundant memory cell for relieving a defect existing in the main memory; an identification number designation terminal for storing an identification number corresponding to the main memory cell; an address terminal for receiving the identification number; and a redundant row selector circuit and a redundant column selector circuit for performing allocation so as to replace a defective memory space of the main memory cell with a memory space of the redundant memory cells. The redundant selector circuits allocate a memory space corresponding to the defect of the main memory cell to the redundant memory cells when the identification number received from the address terminal coincides with the identification number of the identification number specification terminal.
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Nguyen Tan T.
Sharp Kabushiki Kaisha
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