Memory apparatus

Details Memory apparatus Memory apparatus

1992-12-22

1994-12-20

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Multiple port access

36523009, 36518912, 365239, 365240, G11C 800

Patent

active

053748514

ABSTRACT:
In a memory device, data stored in memory cells bridging memory cell columns for two lines can be read out in response to an address signal supplied only once. The memory cells (R00-R03), (R10-R13), (R10-R13), (R20-R23)m (R20-R23) and (R30-R33) for the two adjoining lines are connected to common word lines L0, L1, L2. Also, a series of bit lines are sequentially selected by a counter. The data stored in the memory cells bridging the memory cell columns for the two lines can be read out only once by supplying an address signal only one time.

REFERENCES:
patent: 5036489 (1991-07-01), Theobald
patent: 5065368 (1991-11-01), Gupta et al.
patent: 5068904 (1991-11-01), Yamazaki
patent: 5185724 (1993-02-01), Toda
patent: 5260905 (1993-11-01), Mori

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