Memory and test method therefor

Details Memory and test method therefor Memory and test method therefor

1995-08-24

1998-05-26

Decady, Albert

Excavating

371 102, 365201, G06F 1100

Patent

active

057578141

ABSTRACT:
A redundancy implementation circuit has a set of memory cells each storing an address bit of an address identifying a redundant memory location and a set of comparator circuits each connected to compare the address bit stored in a memory cell with an incoming address bit. A switch selectively connects the output of the memory cell to a redundant address line supplying the incoming address bit during a test mode. A redundant address line driver is activated for supplying an incoming address bit onto the redundant address line in a normal mode, and a test line output driver is connected to the redundant address line in a test mode for utilising the redundant address line to supply test signals onto a test path.

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Office Action from Japanese Patent Application 214493/1995.

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